Synthesis for Control Dominated Circuits

The investigation of efficient synthesis methods for complex control dominated ASICs using library resources including data-path generators is explored in this book. The first chapter addresses the synthesis of complex controllers and includes some novel aspects such as new models (tokenized model, Petri net, etc...), efficient use of ROM and PLA generators for ultra large microcoded controllers and extensions to communication finite state machines including parallel and hierarchical controllers. The second chapter focuses on data-path generation and synthesis, including discussion of the respective advantages of standard cell based solutions versus dedicated bit sliced architectures and automatic synthesis methods dedicated to data-path. Synthesis methods of ASICs described at an RTL level and having as the target precisely circuits made up of a controller and a data-path are considered in the third chapter. The fourth and last chapter focuses on layout synthesis for modules or library block generation, from the basic problem of the automatic layout generation of complex MOS cells, to the generation of regular modules (arithmetic blocks and PLA), to library characterization and design portability.