Beschrijving
This book constitutes the refereed proceedings of the 10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000, held in Göttingen, Germany in September 2000.
The 33 revised full papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in sections on RTL power modeling, power estimation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient technologies, design of multimedia processing applications, adiabatic design and arithmetic modules, and analog-digital circuit modeling.
The 33 revised full papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in sections on RTL power modeling, power estimation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient technologies, design of multimedia processing applications, adiabatic design and arithmetic modules, and analog-digital circuit modeling.
Boekdetails
Formaat
Paperback
Pagina's
338 pagina's
Taal
Engels
Gepubliceerd
Sep 1, 2000
Uitgever
Springer
ISBN-10
3540410686
ISBN-13
9783540410683