Verification Methodology Manual for SystemVerilog
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Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.
Format
Taschenbuch
Seiten
520 Seiten
Sprache
Englisch
Veröffentlicht
Dec 5, 2014
Verlag
Springer
Ausgaben
3 Ausgaben
ISBN-10
1461498139
ISBN-13
9781461498131